The present invention relates to a semiconductor memory device, and more particularly to a circuit for substituting for a defective memory cell of a semiconductor memory device with a redundancy cell.
Generally, a semiconductor memory device has a plurality of memory cells arranged in rows and columns, and as memory capacity increases, more such memory cells are added. Increasing memory capacity increases the probability of defective memory cells being present, and even if just one memory cell is defective, the entire chip cannot be used. In view of this, an inevitable fact follows: as the memory capacity becomes large, the yield of manufactured semiconductor memory devices deteriorates.
Accordingly, in order to raise the yield of manufactured semiconductor memory devices, rows and columns of a redundancy cell array are arranged as part of a standard memory cell array, so that a chip can be used regardless of existing defective memory cells. The yield is improved by substituting for portions of the defective cell array with a column or row from the redundancy memory cell array.
The redundancy method installs redundant memory cells to be substituted at connected positions adjacent to the chip's normal memory cell array. When the address of a defective cell is marked by blowing the metal or polysilicon fuses corresponding to the row (or column) of a defective cell in the normal memory cell array, the operation of the address decoder of a normal row (or column) is intercepted and the row (or column) of a substituted redundant cell is selected.
Generally, semiconductor memory cell constitution (such as in DRAM devices) consists of two states of data topology, corresponding to the arrangement and composition of the memory cell array. That is, one half of the memory cell array equals the output data's state to be read and written, while the other half corresponds to the complement data's state.
Similarly, since the redundant memory cell is constituted and installed as a part of a normal memory cell array in the periphery of a normal memory cell array, the data topology state of the row (or column) of each redundant memory cell can be fixed to one of the above two data topology states. When the defective normal memory cell array and the redundant memory cell array are substituted through a repair, one, two, four or eight rows or columns are substituted at the same time, and when such a block forms one or two redundant memory cell arrays or more, the redundant memory cell array substituted for the defective normal memory cell array is randomly substituted, and as a result, the data state of the substituted redundant cell may be different from the original data state.
Also, if a redundant memory cell which can be substituted according to the address of the cell to be repaired is fixed to match the data state, the efficiency of the redundant cell is reduced. And if the redundant memory cell is used regardless of the data state, the data states of redundant memory cell and the substituted normal memory cell are changed.